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This section describes how FPGA bitstreams are generated and how new projects are created.
This section describes how the bitstream of an example of the SDK is created with Xilinx ISE.
This section explain how an new project is created
1. In the ISE menu: 'File' → 'New Project'
2. Enter a project name (e.g. myProject) and the location of the new project:
3. Select the device settings from the following table below and choose the Simulator / Language (usually “Modelsim-SE VHDL” or “Modelsim-SE Verilog”)
USB-FPGA Module | Family | Device | Package | Speed |
---|---|---|---|---|
1.2 | Spartan 3 | XC3S400 | TQ144 | -4 (or -5 for deluxe variant) |
1.11a | Spartan 6 | XC6SLX9 | FTG256 | -2 |
1.11b | Spartan 6 | XC6SLX16 | FTG256 | -2 |
1.11c | Spartan 6 | XC6SLX25 | FTG256 | -2 or -3 |
4. Create new sources if desired. Usually it is more comfortable to use sources form another project as starting point. This can be done in the next dialog box. (step 5.)
5. Add existing sources here. If you use sources form another project (as starting point) check the 'Copy to Project' boxes.
6. Verify the summary and click 'FINISH'.
7. The new project is created. The sources can be opened by double-clicking on it.
The SDK package contains several more or less sophisticated examples which can be used as starting point for own applications.
There are many VHDL tutorials available in the Internet. One of them (which is much more than just a tutorial) is VHDL Tutorial from Jan van der Spiegel. Other ones can be found using Goolge.