This is an old revision of the document!
This section describes how FPGA bitstreams are generated and how new projects are created.
This section describes how the bitstream of an example of the SDK is created with Xilinx ISE.
This section explain how an new project is created
USB-FPGA Module | Family | Device | Package | Speed |
---|---|---|---|---|
1.2 | Spartan 3 | XC3S400 | TQ144 | -4 (or -5 for deluxe variant) |
The SDK package contains several more or less sophisticated examples which can be used as starting point for own applications.
There are many VHDL tutorials available in the Internet. One of them (which is much more than just a tutorial) is VHDL Tutorial from Jan van der Spiegel. Other ones can be found using Goolge.