First steps with ISE

This section describes how FPGA bitstreams are generated and how new projects are created.

This section describes how the bitstream of an example of the SDK is created with Xilinx ISE.

1. Start the Xilinx ISE
2. In the menu: 'File' → 'Open Project' → select the .xise project file in the 'fpga' sub-directory the the example and click 'Open'
3. Single-click on the main source file in the source hierarchy field (1) and double click on 'Generate Programming File' in the Processes view (2):
   
4. The Bitstream is stored in a bit file, e.g. ucecho.bit. These files can be uploaded via USB using the FWLoader utility or using the API (see the ucecho example) or via JTAG e.g. using the Xilinx Impact tool by clicking on 'Configure Target Device' in the processes view.
   

This section explain how an new project is created

1. In the ISE menu: 'File' → 'New Project'
2. Enter a project name (e.e. myProject) and the location of the new project
3. Select the device settings from the following table <wrap>

^ USB-FPGA Module ^ Family ^ Device ^ Package ^ Speed ^

</wrap>

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The SDK package contains several more or less sophisticated examples which can be used as starting point for own applications.

There are many VHDL tutorials available in the Internet. One of them (which is much more than just a tutorial) is VHDL Tutorial from Jan van der Spiegel. Other ones can be found using Goolge.