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--- en:ztex_boards:ztex_fpga_boards:first_steps_with_ise [2010/12/05 17:35] – 84.181.69.213
+++ en:ztex_boards:ztex_fpga_boards:first_steps_with_ise [2016/08/18 07:05] (current) – gelöscht stefan
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-====== First steps with ISE ======
-This section describes how FPGA bitstreams are generated and how new projects are created.
-====== Generating the Bitstream ======
-This section describes how the bitstream of an example of the SDK is created with Xilinx ISE.
-  - Start the Xilinx ISE
-  - In the menu: 'File' -> 'Open Project' -> select the .xise project file in the 'fpga' sub-directory the the example and click 'Open'
-  - Single-click on the main source file in the source hierarchy field (1) and double click on 'Generate Programming File' in the Processes view (2): \\ {{:en:ztex_boards:ztex_fpga_boards:ise-intro-1-1.png|ISE Intro: Generating the Bitstream 1}}
-  - The Bitstream is stored in a bit file, e.g. ucecho.bit. These files can be uploaded via USB using the [[en:software:fwloader|FWLoader]] utility or using the API (see the [[en:projects:ucecho_fpga#java_host_softwareucechojava|ucecho example]]) or via [[en:ztex_boards:ztex_fpga_boards:jtag|JTAG]] e.g. using the Xilinx Impact tool by clicking on 'Configure Target Device' in the processes view. \\  {{:en:ztex_boards:ztex_fpga_boards:ise-intro-1-2.png|ISE Intro: Generating the Bitstream 2}}
-====== Crating a new project ======
-===== Examples =====
-The [[en:software:package_contents|SDK package]] contains several more or less sophisticated examples which can be used as
-starting point for own applications.
-===== VHDL tutorials =====
-There are many VHDL tutorials available in the Internet. One of them (which is much more than just a tutorial) is
-[[http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html|VHDL Tutorial from Jan van der Spiegel]].
-Other ones can be found using [[http://www.google.com/search?q=vhdl+tutorial|Goolge]].
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