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Due to many requests for LTC mining software for ZTEX FPGA Boards I took a deeper look into the scrypt algorithm. The goal was to estimate development effort and achievable hash rates. Results are presented here.
In order to prevent confusions and questions: ZTEX does not plan to develop Litecoin mining software.
A description of the scrypt algorithm can be found at http://tools.ietf.org/html/draft-josefsson-scrypt-kdf-01, an example implementation at https://github.com/litecoin-project/litecoin/blob/master/src/scrypt.c.
Easiest way to implement this are non-pipelined loops. Limiting factor is the amount of vectors n which fit into the block RAM. Total hash rate would be
f r = n * --------- 140,000/H
On XC6SLX150 n is 4 and estimated f is 300MHz. Hash rate would be approximately 8.6 KH/s.
One implementation approach would be fully unrolling the scryptBlockMix function. This results in an 68 stage pipeline and approx. 8.7 MByte memory requirement. Pipeline clock is defined by the memory read / write delay. Altogether, hash rate is limited by memory bandwidth b:
b r = ---------- 262272 B/H
On ZTEX-USB FPGA Modules 1.15 b is 1600 MB/s. Maximum achievable hash rate according to the equation above would be 61 kH/s. Due to latencies of DRAM a hash rate of 50 Kh/s is more realistic.
In order to prevent confusions and questions: ZTEX does not plan to develop Litecoin mining software.