Differences

This shows you the differences between two versions of the page.

--- en:ztex_boards:ztex_fpga_boards:litcoin_mining_on_fpga [2013/07/15 14:52] – 84.181.59.227
+++ en:ztex_boards:ztex_fpga_boards:litcoin_mining_on_fpga [2017/01/21 14:25] (current) – removed stefan
@@ Line 1: / Line 1: @@
-====== Litecoin Mining on FPGA's ======
-Due to many requests for LTC mining software for ZTEX FPGA Boards I took a deeper look into the scrypt algorithm. The goal was to estimate the development effort and the hash rates which can be expected. Results are presented here.
-**In order to prevent confusions and questions: ZTEX does not plan to develop Litecoin mining software.**
-A description of the scrypt algorithm can be found at [[http://tools.ietf.org/html/draft-josefsson-scrypt-kdf-01]], an example implementation at
-[[https://github.com/litecoin-project/litecoin/blob/master/src/scrypt.c]].
-  * The PBKDF2-HMAC-SHA-256 function can be neglected here. The computations can be done parallelly to the other computations and a single 64 cycle per SHA256 transformation loop is sufficient for many scryptROMix loops
-  * Due to decencies of intermediate results each scryptROMix loop requires about 140,000 computation steps
-  * Each scryptROMix loop (or pipeline stage) requires one 128 KByte vector (which has to be stored in some kind of RAM)
-===== Approach 1: FPGA implementation using Block RAM =====
-Easiest way to implement this are non-pipelined loops. Limiting factor is the amount of vectors n which fit into the block RAM. Total hash rate would be
-<code>
-            f
-r = n * ---------
-,000/H
-</code>
-On XC6SLX150 n is 4 and estimated f is 300MHz. **Hash rate would be approximately 8.6 KH/s.**
-===== Approach 2: FPGA implementation using external RAM =====
-One implementation approach would be fully unrolling the scryptBlockMix function. This results in an 68 stage pipeline and 8704 MByte memory. Pipeline clock if defined by the memory read / write delay. Alltogether, hash rate is limited by memory bandwidth b:
-<code>
-        b
-r = ----------
-B/H
-</code>
-On [[http://www.ztex.de/usb-fpga-1/usb-fpga-1.15.e.html|ZTEX-USB FPGA Modules 1.15]] b is 1600 MB/s. Hash rate limit according to the equation above would be
-kH/s. Due to latencies of DRAM **a hash rate of 50 Kh/s** are more realistic.
-**In order to prevent confusions and questions: ZTEX does not plan to develop Litecoin mining software.**