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| en:ztex_boards:ztex_fpga_boards:litcoin_mining_on_fpga [2013/10/13 00:12] – 1600*1000*1000/262272=6100,53 80.99.0.42 | en:ztex_boards:ztex_fpga_boards:litcoin_mining_on_fpga [2017/01/21 14:25] – [Approach 2: FPGA implementation using external RAM] stefan | ||
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| On XC6SLX150 n is 4 and estimated f is 300MHz. **Hash rate would be approximately 8.6 KH/s.** | On XC6SLX150 n is 4 and estimated f is 300MHz. **Hash rate would be approximately 8.6 KH/s.** | ||
| - | ===== Approach 2: FPGA implementation using external RAM ===== | ||
| - | One implementation approach would be fully unrolling the scryptBlockMix function. This results in an 68 stage pipeline and approx. 8.7 MByte memory requirement. Pipeline clock is defined by the memory read / write delay. Altogether, hash rate is limited by memory bandwidth b: | ||
| - | < | ||
| - | b | ||
| - | r = ---------- | ||
| - | 262272 B/H | ||
| - | </ | ||
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| - | On [[http:// | ||
| - | 6.1 kH/s. Due to latencies of DRAM **a hash rate of 5.0 Kh/s** is more realistic. | ||
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| - | **In order to prevent confusions and questions: ZTEX does not plan to develop Litecoin mining software.** | ||
