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en:ztex_boards:ztex_fpga_boards:litcoin_mining_on_fpga [2013/07/15 14:45] – 84.181.59.227 | en:ztex_boards:ztex_fpga_boards:litcoin_mining_on_fpga [2017/01/21 14:25] – [Approach 2: FPGA implementation using external RAM] stefan | ||
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====== Litecoin Mining on FPGA's ====== | ====== Litecoin Mining on FPGA's ====== | ||
- | Due to many requests for LTC mining software for ZTEX FPGA Board we took a deeper | + | Due to many requests for LTC mining software for ZTEX FPGA Boards I took a deeper |
**In order to prevent confusions and questions: ZTEX does not plan to develop Litecoin mining software.** | **In order to prevent confusions and questions: ZTEX does not plan to develop Litecoin mining software.** | ||
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* The PBKDF2-HMAC-SHA-256 function can be neglected here. The computations can be done parallelly to the other computations and a single 64 cycle per SHA256 transformation loop is sufficient for many scryptROMix loops | * The PBKDF2-HMAC-SHA-256 function can be neglected here. The computations can be done parallelly to the other computations and a single 64 cycle per SHA256 transformation loop is sufficient for many scryptROMix loops | ||
* Due to decencies of intermediate results each scryptROMix loop requires about 140,000 computation steps | * Due to decencies of intermediate results each scryptROMix loop requires about 140,000 computation steps | ||
- | * Each scryptROMix loop (or pipeline stage) requires one 128 KByte vector (which has to be stored in some kind of RAM) | + | * Each scryptROMix loop (or pipeline stage) requires one 128.125 KByte vector (which has to be stored in some kind of RAM) |
===== Approach 1: FPGA implementation using Block RAM ===== | ===== Approach 1: FPGA implementation using Block RAM ===== | ||
- | Easiest way to implement this are is a non-pipelined | + | Easiest way to implement this are non-pipelined |
< | < | ||
f | f | ||
- | r = n * ---------- | + | r = n * --------- |
140,000/H | 140,000/H | ||
</ | </ | ||
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On XC6SLX150 n is 4 and estimated f is 300MHz. **Hash rate would be approximately 8.6 KH/s.** | On XC6SLX150 n is 4 and estimated f is 300MHz. **Hash rate would be approximately 8.6 KH/s.** | ||
- | ===== Approach 2: FPGA implementation external RAM ===== | ||
- | |||
- | One implementation approach would be fully unrolling the scryptBlockMix function. This results in an 68 stage pipeline and 8704 MByte memory. Pipeline clock if defined by the memory read / write delay. Alltogether, | ||
- | < | ||
- | b | ||
- | r = ---------- | ||
- | 262144 B/H | ||
- | </ | ||
- | |||
- | On [[http:// | ||
- | 61 kH/s. Due to latencies of DRAM **a hash rate of 50 Kh/s** are more realistic. | ||
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- | In order to prevent confusions and questions: ZTEX does not plan to develop Litecoin mining software. | ||