====== memfifo Example for Series 2 FPGA Boards ======

It is a more complex example for [[http://www.ztex.de/index.html|Series 2 FPGA Boards]] which demonstrates

  * High speed EZ-USB -> FPGA transfers using the Slave FIFO interface
  * High speed FPGA -> EZ-USB transfers using the Slave FIFO interface
  * Usage of external SDRAM (if available on FPGA Board) or internal BRAM

===== Description =====

This example uses the [[en:software:default_firmware|Default Firmware]].
A large FIFO is implemented using SDRAM or BRAM, respectively.
Input of this FIFO is either the hi-speed input channel of the default Interface or a test
pattern generator with variable data rate. Data is written to host
using the hi-speed output channel of the Default Interface.

The host software writes the data (in/out mode), reads it back
and verifies it. Several tests are performed in order to test flow 
control, data rates, etc.

Reset is handled through the dedicated reset pin of the Default Interface. Furthermore two GPIOs are used to select the data source:

^ PA1:PA0  ^ Source ^
| 0:0  | Hi-speed input channel of the Default Interface  |
| 0:1  | 48 MByte/s (FX2) or 208 MByte/s (FX3) test pattern generator  |
| 1:0  | 12 MByte/s (Fx2) or 13 MByte/s (FX3) test pattern generator  |
| 1:1  | unused, reserved for testing purposes |


===== Debug Board support =====
The examples can use the [[http://www.ztex.de/usb-fpga-2/debug.e.html|Debug Board]] to output some information (its usage is not required). 

  * **LED1:** Debug/status output, see SW10
  * **LED2-3:** Fill level of the DRAM FIFO
  * **SW10**
    * **on:** status signals from dram_fifo module
    * **off:** status signals from top level module

===== HDL Modules =====
The HDL sources are divided into 4 modules:

  * **1. ''ezusb_io.v'':** Part of the [[en:software:default_firmware#hdl_modules|Default interface]]. Implements high-speed communication.
  * **2. ''ezusb_gpio.v'': ** Part of the [[en:software:default_firmware#hdl_modules|Default interface]]. Implements GPIO's for mode selection.
  * **3a. ''dram_fifo.v'':** Implements a large FIFO  from all SDRAM, if available
  * **3b. ''bram_fifo.v'':** Implements a FIFO  from all BRAM, if no SDRAM is available
  * **4. ''memfifo.v''/''memfifo.vhdl'':** The top level module glues everything together.

Modules 1., 2., 3a. and 3b. are re-usable. Their instantiation is demonstrated in the top level module which is available in Verilog and VHDL.
Descriptions can be found on the [[en:software:default_firmware#hdl_modules|Default interface]] page and below.

==== dram_fifo / bram_fifo ====

This module implements a FIFO which is built using SDRAM (dram_fifo) or Block RAM (BRAM, bram_fifo).

Three variants exist in the SDK

^ FPGA type  ^ Memory type  ^ Module  ^  FPGA Board  ^
| Artix 7  | DDR3 SDRAM | dram_fifo  | [[http://www.ztex.de/usb-fpga-2/usb-fpga-2.13.e.html|USB-FPGA Module 2.13]]\\ [[http://www.ztex.de/usb-fpga-2/usb-fpga-2.14.e.html|USB-FPGA Module 2.14]]\\ [[http://www.ztex.de/usb-fpga-2/usb-fpga-2.18.e.html|USB-FPGA Module 2.18]]  |
| Spartan 6 | DDR SDRAM | dram_fifo  | [[http://www.ztex.de/usb-fpga-2/usb-fpga-2.04.e.html|USB-FPGA Module 2.04]]  |
| all  | Block RAM | bram_fifo  | [[http://www.ztex.de/usb-fpga-2/usb-fpga-2.16.e.html|USB-FPGA Module 2.16]]\\ [[http://www.ztex.de/usb-fpga-2/usb-fpga-2.01.e.html|USB-FPGA Module 2.01]] |

The FIFO interface is not 100% compatible, but the protocol is always the same: it's a FWFT (forst word falls through) FIFO as described in [[http://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf|Xilinx UG473]]. The common part of the interface is describes by the following code snippet, the differences are listed below.

<code verilog>
module .ram_fifo # (
	input reset,		// asynchronous reset input
	// FIFO protocol equal to FWFT FIFO in "7 Series Memory Resources" user guide (ug743)
	// input interface of the FIFO
        input [31:0] DI,        // input data, 128 bit with Artix 7 + SDRAM, otherwise 32 bit
                                // must be hold while FULL is asserted
        output FULL,            // full flag
        output reg WRERR,       // write error
        input WRCLK,            // write clock
        input WREN,             // write enable

	// output interface of the FIFO
	output reg [31:0] DO,   // output data, 128 bit with Artix 7 + SDRAM, otherwise 32 bit
	output reg EMPTY,       // empty flag, can be used as data valid indicator
        output reg RDERR,       // read error
        input RDCLK,            // read clock
        input RDEN              // read enable
    );
</code>

=== Differences ===

  * Word width (ports ''DI'' and ''DO'') is 128 Bit on FPGA Boards with Artix 7 and external RAM, 32 Bit on all other FPGA Boards
  * Port definition of SDRAM implementations includes hardware pins (see examples)
  * SDRAM implementations have a system clock input (''FXCLK'') and at least one clock output with adjustable parameters (see comments in the examples)
  * The amount of BRAM blocks used is adjusted by the parameter ''BRAM_N'' (bram_fifo only)
  * On FPGA Boards with Artix 7 and external RAM four BRAM blocks are used by the core to buffer the input and output. All parameters are exported, see comments of the examples and [[http://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf|Xilinx UG473]].