===== LEON3 SPARC processor ====== The [[http://www.gaisler.com/cms/index.php?option=com_content&task=view&id=13&Itemid=53|LEON3]] is a synthesisable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The model is highly configurable, and particularly suitable for system-on-a-chip (SOC) designs. The full source code is available under the GNU GPL license, allowing free and unlimited use for research and education. LEON3 is also available under a low-cost commercial license, allowing it to be used in any commercial application to a fraction of the cost of comparable IP cores. This project explains how a LEON3 processor can be implemented on a ZTEX Modules: ^ Module ^ FPGA ^ CPU cores ^ MMU ^ FPU ^ Utilization ^ Linux ^ | [[http://www.ztex.de/usb-fpga-1/usb-fpga-1.11.e.html|1.11c]] | LX25 | 1 | no | no | 54% | no | | [[http://www.ztex.de/usb-fpga-1/usb-fpga-1.11.e.html|1.11c]] | LX25 | 1 | yes | yes | 88% | yes | | [[http://www.ztex.de/usb-fpga-1/usb-fpga-1.15.e.html|1.15b]] | LX75 | 2 | yes | yes | 53% | yes, SMP | ===== Download the fresh Source ===== * Download and unpack [[http://www.gaisler.com/products/grlib/grlib-gpl-1.1.0-b4113.zip|LEON3/GRLIB source code 1.1.0-b4113]] * Download and unpack into grlib root dir [[http://www.gaisler.com/products/grlib/grlib-netlists-1.1.0.tar.gz|GRFPU netlists]] and [[http://strijar.ru/ztex/leon3-ztex.zip|LEON3 ZTEX port]] * Change dir to designs/leon3-ztex-ufm-xc6slx25 ===== Synthesize the design ===== The design uses the Xilinx MIG memory interface with an AHB-2.0 interface. The MIG source code cannot be distributed due to the prohibitive Xilinx license, so the MIG must be re-generated with coregen before simulation and synthesis can be done. To generate the MIG do as follows: make mig This will ONLY work with ISE-13 installed, and the XILINX variable properly set in the shell. To synthesize the design, do make ise ===== EZ-USB FX2 Firmware ===== No special firmware is required in order to run LEON3. The [[en:ztex_boards:ztex_fpga_boards:standalone|standalone firmware]] from the ZTEX SDK can be used as dummy firmware and to allow Bitstream uploading via USB. ===== Load bitstream ===== The bitstream can be uploaded via USB using [[en:software:FWLoader]] or via [[en:ztex_boards:ztex_fpga_boards:jtag|JTAG]] using Xilinx Impact. ===== Connect serial console ===== In order to verify the functionality of the LEON3 a serial adapter cable need to be connected to the FPGA Board. By default serial port has a baud rate **38400** By default, the serial port is connected to the following pins: ^ Name ^ FPGA ball ^ Pin of the FPGA Board ^ Pin at the Experimental board ^ | TX | C13 | A13 | A13 | | RX | A14 | A12 | A12 | If other pins are preferred, lines around line 9 need to be changed. ===== DSU - Debug Support Unit ===== To simplify debugging on target hardware, the LEON3 processor implements a debug mode during which the pipeline is idle and the processor is controlled through a special debug interface. The LEON3 Debug Support Unit (DSU) is used to control the processor during debug mode. By default, the DSU serial port is connected to the following pins: ^ Name ^ FPGA ball ^ Pin of the FPGA Board ^ Pin at the Experimental board ^ | TX | E11 | A15 | A15 | | RX | D12 | A14 | A14 | You can connect DSU via [[en:ztex_boards:ztex_fpga_boards:jtag|JTAG]] also ===== GRMON - Debug Monitor for LEON systems ====== GRMON is a general debug monitor for the LEON processor, and for SOC designs based on the GRLIB IP library. Download and unpack from [[http://www.gaisler.com/cms/index.php?option=com_content&task=view&id=190&Itemid=124|GRMON page]] evaluation version for Linux and Windows Start gromon with uart or jtag (USB or LPT): * -uart /dev/ttyUSB0 -baud 460800 * -xilusb * -jtag Output from GRMON is: GRMON LEON debug monitor v1.1.49 evaluation version Copyright (C) 2004-2011 Aeroflex Gaisler - all rights reserved. For latest updates, go to http://www.gaisler.com/ Comments or bug-reports to support@gaisler.com This evaluation version will expire on 20/1/2012 using port /dev/ttyUSB0 @ 460800 baud Device ID: : 0x601 GRLIB build version: 4108 initialising ............ detected frequency: 74 MHz Component Vendor LEON3 SPARC V8 Processor Gaisler Research AHB Debug UART Gaisler Research AHB Debug JTAG TAP Gaisler Research AHB/APB Bridge Gaisler Research LEON3 Debug Support Unit Gaisler Research AHB static ram Gaisler Research Xilinx MIG DDR2 controller Gaisler Research AHB ROM Gaisler Research Generic APB UART Gaisler Research Multi-processor Interrupt Ctrl Gaisler Research Modular Timer Unit Gaisler Research General purpose I/O port Gaisler Research Use command 'info sys' to print a detailed report of attached cores grlib> info sys 00.01:003 Gaisler Research LEON3 SPARC V8 Processor (ver 0x0) ahb master 0 01.01:007 Gaisler Research AHB Debug UART (ver 0x0) ahb master 1 apb: 80000700 - 80000800 baud rate 460800, ahb frequency 74.00 02.01:01c Gaisler Research AHB Debug JTAG TAP (ver 0x1) ahb master 2 01.01:006 Gaisler Research AHB/APB Bridge (ver 0x0) ahb: 80000000 - 80100000 02.01:004 Gaisler Research LEON3 Debug Support Unit (ver 0x1) ahb: 90000000 - a0000000 stack pointer 0x43fffff0 CPU#0 win 8, V8 mul/div, srmmu, lddel 2, GRFPU-lite icache 1 * 4 kbyte, 32 byte/line dcache 1 * 4 kbyte, 32 byte/line 03.01:00e Gaisler Research AHB static ram (ver 0xc) ahb: a0000000 - a0100000 4 kbyte AHB ram @ 0xa0000000 04.01:06b Gaisler Research Xilinx MIG DDR2 controller (ver 0x0) ahb: 40000000 - 44000000 apb: 80000500 - 80000600 DDR2: 64 Mbyte 06.01:01b Gaisler Research AHB ROM (ver 0x0) ahb: 00000000 - 00100000 01.01:00c Gaisler Research Generic APB UART (ver 0x1) irq 2 apb: 80000100 - 80000200 baud rate 38381 02.01:00d Gaisler Research Multi-processor Interrupt Ctrl (ver 0x3) apb: 80000200 - 80000300 03.01:011 Gaisler Research Modular Timer Unit (ver 0x0) irq 8 apb: 80000300 - 80000400 8-bit scaler, 2 * 32-bit timers, divisor 74 0b.01:01a Gaisler Research General purpose I/O port (ver 0x1) apb: 80000b00 - 80000c00 grlib> ===== Run stanalone samples ===== Load precompiled Dhrystone test by GRMON grlib> lo ../samples/dhry.exe section: .text at 0x40000000, size 49616 bytes section: .data at 0x4000c1d0, size 2408 bytes total size: 52024 bytes (362.3 kbit/s) read 251 symbols entry point: 0x40000000 grlib> run Program exited normally. grlib> Serial console out is: Execution starts, 400000 runs through Dhrystone Microseconds for one run through Dhrystone: 9.3 Dhrystones per Second: 107142.9 Dhrystones MIPS : 61.0 How [[en:projects:leon3:standalone|build and run other samples]] ===== Run Linux ===== How [[en:projects:leon3:linux|build and run Linux-3.0]] ===== Configure design ===== You can change design configuration of LEON3 through configuration utility. From dir designs/leon3-ztex-ufm-xc6slx25 do: make xconfig ==== Clock frequency ==== By default LEON3 clock is 72Mhz. But it may be more up to 90MHz. You can change the frequency of LEON3 through configuration utility. Select "Clock generation" and change: * Clock multiplication factor 15 * Clock division factor 8 To note, the time of synthesis (for 90Мгц) about 2.5-3 hours! ==== Save area ==== To save area, you can disable the MMU, FPU ==== Rebuild design ==== Press "Main Menu" and "Save and Exit". Rebuild design: make clean make scripts make ise ===== Prebuild bit streams ====== LEON3 V8 with MMU and FPU: * [[http://strijar.ru/ztex/leon3mp_lx25_72mhz.bit|LX25 72Mhz]] * [[http://strijar.ru/ztex/leon3mp_lx25_90mhz.bit|LX25 90Mhz]] * [[http://strijar.ru/ztex/leon3mp_lx75_72mhz_smp.bit|LX75 72Mhz SMP (2 core)]]